1. Field of the Invention
The present invention relates to a high-speed external memory system, and more particularly to a high-speed external memory system which permits the execution of a read/write operation in a program mode during data transfer from the external memory system to a central processing unit in a direct memory access mode.
2. Description of the Prior Art
A conventional type of external memory system which is controlled by a microprogram has an arrangement as illustrated in FIG. 2. A description will be given of its operation in the program mode and the direct memory access (hereinafter referred to as DMA) mode.
A description will be given first of starting the external memory system while in the program mode. When supplied with a selected address from the external memory system via a data bus e from a central processing unit (hereinafter referred to as the CPU) 1, an input and output address matching circuit (IOA math) 2 compares the address with an address of the external memory system inputted from an input and output address generator 3 and, in case of coincidence, provides a start signal to a sequence controller (SEQ CTL) 4. Then the sequence controller 4 applies a control signal to a microprogram control M which comprises a sequencer (SEQ) 5, a control memory (CM) 6 and a control memory instruction register (CMIR) 7. The sequencer 5 responds to the control signal from the sequence controller 4 to sequentially deliver control instructions from the control memory 6 to the control memory instruction register 7. The control memory instruction register 7 has the function of storing and executing the control instructions from the control memory 6. When starting the microprogram, the control memory instruction register 7 reports the acceptance of the access to the CPU 1 via an IOM (Input and Output Mode) control 8 and an IOM signal line d. CPU 1 recognizes the acceptance of the access and sends an order specifying the execution of a memory access by the external memory system. via a CPM (Central Processor Mode) signal line c to the sequence controller 4 system. Then the sequence controller 4 restarts the sequencer 5. When this order is determined by the microprogram control M to be normal, the decision result is issued from the control memory instruction register 7 via the IOM control 8 to the CPU 1 to acknowledge the acceptance of the order, and the microprogram control M starts an operation following the order of the CPU 1. If this order is, for example, a one word readout order, address information is sent by the microprogram control M from the data bus e to the location address register (LAR) and the microprogram control M thereby provides the address information to a memory 10. Data read out from the memory 10 based on the address information is provided to a data buffer register (DBR) 11. The data thus loaded in the data buffer register 11 is checked by an error correcting circuit (ECC) 12 and is loaded again in the data buffer register 11. The microprogram control M applies a data transfer instruction via the IOM control 8 to the CPU 1 and instructs the data buffer register 11 to send out the data therefrom to the CPU 1 via the data bus e. The CPU 1 provides the information indicating that it has received the data via the CPM signal line c to the sequence controller 4. Upon reception of this signal by the microprogram control M, the one word readout operation in the program mode comes to an end. In the case where the external memory system receives a DMA order during the execution of the program mode, access the program mode access is stopped and acknowledged by applying acknowledgement for information the reception of the order to the CPU 1 via the CPM signal line c and thereafter the external memory system independently executes an access operation following the DMA order.
Next, in the event that the order given to the external memory system is an order for DMA transfer, a request to transfer is sent from the microprogram control M to the CPU 1 via the IOM control 8 and an RQ (Request) signal line b. When the CPU 1 is ready to receive the request, a request-OK signal is sent back to the external memory via an RQ-OK (Request-OK) signal line a, starting the DMA transfer. In this case, the data transfer from the memory 10 is performed in the same manner as in the program mode. If the quantity of data to be transferred is large, the CPU 1 is occupied by this transfer and results in the CPU processing being stopped for a long period of time. To avoid this, the large quantities data are transferred by steps of several units of data under the control of the microprogram control M and a burst timer 13 is activated after each transfer to provide burst timing control of the microprogram itself, and stops the transfer operation until started by the burst timer 13. During this timing interval, the CPU 1 may execute other processing. Upon completion of the burst timing, the microprogram control M is started by the burst timer 13 to again send the request for the DMA transfer to the CPU 1, and the external memory system resumes the DMA transfer under the control of the microprogram. This operation would be repeated until the predetermined quantity of data are all transferred.
FIG. 3 is a diagram illustrating the data transfer in the conventional external memory system shown in FIG. 2. When performing the DMA transfer, the operation is started by an instruction from the CPU 1 to effect the DMA transfer in accordance with an address loaded in the location address register 9. FIG. 3 illustrates the case where the DMA transfer is accomplished in steps of four words and the burst timing is provided in the interval between the respective DMA transfer operations. During the DMA transfer including the burst timing, the location address register 9 remains busy and even if a request for the program mode transfer occurs, the external memory system cannot accept the request. Upon completion of the DMA transfer of a required quantity of data, a DMA transfer end report is provided to the CPU 1, by which the location address register 9 is released from its busy state, making the external memory system ready for receiving an address in the program mode. When it is necessary to execute the program mode access, an address specified by the program mode is loaded in the location address register 9 and the program mode transfer is accomplished using the specified address.
As described above, according to the prior art, the read/write operation of the external memory in the program mode which occurs during the DMA transfer cannot be performed until after the DMA transfer is completed. In other words, the conventional external memory system is incapable of conducting the read/write operation in the program mode during the operation in the DMA mode, and hence it has a defect in that the processing time is delayed.